TLK2201B_13 Datasheet, PDF (13/24 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

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TLK2201B
TLK2201BI
SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
CLOCK
1.4 V
t_r
t_f
DATA
t_r
80%
50%
20%
t_f
2V
0.8 V
Figure 9. TTL Data I/O Valid Levels for AC Measurement
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
t_r(RBC)
t_f(RBC)
t_r
t_f
t_su(D1)
t_h(D1)
t_su(D2)
t_h(D2)
t_su(D3)
t_h(D3)
PARAMETER
Clock rise time
Clock fall time
Data rise timer
Data fall time
Data setup time (RD0..RD9),
Data valid prior to RBC0 rising)
Data hold time (RD0..RD9),
Data valid after RBC0 rising
Data setup time (RD0..RD4)
Data hold time (RD0..RD4)
Data setup time (RD0..RD9)
Data hold time (RD0..RD9)
TEST CONDITIONS
MIN TYP MAX UNIT
80% to 20% output voltage, C = 5 pF (see Figure 9) 0.3
0.3
1.5
ns
1.5
0.3
1.5
ns
0.3
1.5
TBI normal mode (see Figure 3)
2.5
ns
TBI normal mode (see Figure 3)
2
ns
DDR mode, R_ω = 125 MHz (see Figure 4)
2
ns
DDR mode, R_ω = 125 MHz (see Figure 4)
0.8
ns
TBI half-rate mode, R_ω = 125 MHz (see Figure 2)
2.5
ns
TBI half-rate mode, R_ω = 125 MHz (see Figure 2)
1.5
ns
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
t_su(D4)
t_h(D4)
t_su(D5)
t_h(D5)
t_r, t_f
PARAMETER
Data setup time (TD0..TD9)
Data hold time (TD0..TD9)
Data setup time (TD0..TD9)
Data hold time (TD0..TD9)
TD[0,9] Data rise and fall time
TEST CONDITIONS
TBI modes
DDR modes
See Figure 9
(1) Measured at 1.25V (midpoint of V_IL and V_IH) with input switching between 0V and V_DD.
MIN
1.6
0.59 ⁽¹⁾
0.7
0.5
TYP
MAX UNIT
ns
ns
2 ns
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