TLK2201B_13 Datasheet, PDF (12/24 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2201B
TLK2201BI
SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
TRANSMITTER/RECEIVER CHARACTERISTICS
V_(cm)
I_lkg(R)
C_I
t_(TJ)
t_(DJ)
t_r, t_f
PARAMETER
Vod = |TxD–TxN|
Transmit common mode voltage range
Receiver Input voltage requirement,
Vid = |RxP - RxN|
Receiver common mode voltage range,
(RxP + RxN)/2
Receiver input leakage current
Receiver input capacitance
Serial data total jitter (peak-to-peak)
Serial data deterministic jitter (peak-to-peak)
Differential signal rise, fall time (20% to 80%)
Serial data jitter tolerance minimum required
eye opening, (per IEEE-802.3 specification)
Receiver data acquisition lock time from
powerup
TEST CONDITIONS
Rt = 50 Ω
Rt = 75 Ω
Rt = 50 Ω
Rt = 75 Ω
Differential output jitter, Random +
deterministic, PRBS pattern,
R_ω = 125 MHz
Differential output jitter, PRBS pattern,
R_ω = 125 MHz
R_L = 50 Ω, C_L = 5 pF,
See Figure 7 and Figure 8
Differential input jitter, Random +
deterministic,
R_ω = 125 MHz
Data relock time from loss of synchronization
t_{d(Tx latency)}
Tx latency
t_{d(Rx latency)} Rx latency
TBI modes See Figure 1
DDR
mode
TBI modes See Figure 6
DDR
mode
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MIN
600
800
1000
1000
TYP
850
1050
1250
1250
MAX
1100
1200
1400
1400
UNIT
mV
mV
200
1600 mV
1000 1250 2250 mV
–350
350 µA
2 pF
0.24 UI
0.12 UI
100
250 ps
0.25
UI
500 µs
1024
Bit
times
19
20
29
30 ^UI
21
31
27
34 ^UI
TX+
t_r
80% ^{∼ V}
50%
20% _{∼ V}
t_f
80% ^{∼ V}
TX−
50%
20% ∼ V
t_f
t_r
80%
VOD
20%
∼ 1V
0V
∼ −1V
Figure 7. Differential and Common-Mode Output Voltage
Definitions
C_L
5 pF
C_L
5 pF
50 Ω
50 Ω
Figure 8. Transmitter Test Setup
12
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