TLC59108F_15 Datasheet, PDF (13/37 Pages) Texas Instruments – 8-Bit FM+ I2C Bus LED Driver

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TLC59108F
SLDS162B – MARCH 2009 – REVISED DECEMBER 2015
Programming (continued)
8.5.6.1 Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 10).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 10. Bit Transfer
8.5.6.2 Start and Stop Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the Stop condition (P) (see Figure 11).
SDA
SDA
SCL
S
P
SCL
Start Condition
Stop Condition
Figure 11. Start and Stop Conditions
8.5.7 System Configuration
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master and the devices which are controlled by the master are the slaves (see Figure 12).
SDA
SCL
Master
Transmitter/
Receiver
Slave Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I²C Bus
Multiplexer
Slave
Figure 12. System Configuration
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