LP38852-ADJ_16 Datasheet, PDF (13/33 Pages) Texas Instruments – 1.5-A Fast-Response High-Accuracy Adjustable LDO Linear Regulator

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Feature Description (continued)
LP38852-ADJ
SNVS482F – JANUARY 2007 – REVISED DECEMBER 2015
Figure 22. Typical C_SS vs C_OUT Values
The C_SS capacitor must be connected to a clean ground path back to the device ground pin. No components,
other than C_SS, should be connected to the SS pin, as there could be adverse effects to V_OUT.
If the soft-start function is not needed the SS pin must be left open, although some minimal capacitance value is
always recommended.
7.3.5 Setting The Output Voltage
The output voltage is set using the external resistive divider R1 and R2. (Refer to the Figure 23.) The output
voltage is given by Equation 2:
V_OUT
=
V_ADJ
x
§
¨©¹⁺
§
¨
©
R1
R2
¹·¸_¹·¨
(2)
The resistors used for R1 and R2 must be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of V_ADJ is specified, the use of low quality
resistors for R1 and R2 can easily produce a V_OUT value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F_Z pole set by R1 and
C_FF.
((R1 x R2) / (R1 + R2)) ≤ 10 kΩ
(3)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C_FF, for a range of V_OUT values. Other values of R1, R2, and C_FF are available that give
similar results.
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