DS90C032QML Datasheet, PDF (13/18 Pages) Texas Instruments – DS90C032QML LVDS Quad CMOS Differential Line Receiver

is in TRI-STATE or in power-off condition. The use of external
biasing resistors provide a small bias to set the differential
input voltage while the line is un-driven, and therefore the re-
ceiver output will be in HIGH state. If the driver is removed
from the bus but the cable is still present and floating, the
unplugged cable can become a floating antenna that can pick
up noise. The LVDS receiver is designed to detect very small
amplitude and width signals and recover them to standard
logic levels. Thus, if the cable picks up more than 10mV of
differential noise, the receiver may respond. To insure that
any noise is seen as commonmode and not differential, a bal-
anced interconnect and twisted pair cables is recommended,
as they help to ensure that noise is coupled common to both
lines and rejected by the receivers.
3. Operation in environment with greater than 10mV dif-
ferential noise
National recommends external failsafe biasing on its LVDS
receivers for a number of system level and signal quality rea-
Pin Descriptions
sons. First, only an application that requires failsafe biasing
needs to employ it. Second, the amount of failsafe biasing is
now an application design parameter and can be custom tai-
lored for the specific application. In applications in low noise
environments, they may choose to use a very small bias if
any. For applications with less balanced interconnects and/or
in high noise environments they may choose to boost failsafe
further. Nationals "LVDS Owner’s Manual provides detailed
calculations for selecting the proper failsafe biasing resistors.
Third, the common-mode voltage is biased by the resistors
during the un-driven state. This is selected to be close to the
nominal driver offset voltage (VOS). Thus when switching be-
tween driven and un-driven states, the common-mode mod-
ulation on the bus is held to a minimum.
For additional Failsafe Biasing information, please refer to
Application Note AN-1194 for more detail.
Pin No. (SOIC)
2, 6, 10, 14
1, 7, 9, 15
3, 5, 11, 13
4
12
16
8
Name
R_I+
R_I−
R_O
EN
EN*
V_CC
Gnd
Description
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
Ground pin
Radiation Environments
Careful consideration should be given to environmental con-
ditions when using a product in a radiation environment.
Total Ionizing Dose
Radiation hardness assured (RHA) products are those part
numbers with a total ionizing dose (TID) level specified in the
Ordering Information table on the front page. Testing and
qualification of these products is done on a wafer level ac-
cording to MIL-STD-883G, Test Method 1019.7, Condition A
and the “Extended room temperature anneal test” described
in section 3.11 for application environment dose rates less
than 0.19 rad(Si)/s. Wafer level TID data is available with lot
shipments.
Single Event Latch-Up and
Functional Interrupt
One time single event latch-up (SEL) and single event func-
tional interrupt (SEFI) testing was preformed according to
EIA/JEDEC Standard, EIA/JEDEC57. The linear energy
transfer threshold (LETth) shown in the Features on the front
page is the maximum LET tested. A test report is available
upon request.
Single Event Upset
A report on single event upset (SEU) is available upon re-
quest.
www.national.com
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