DS90C032QML Datasheet, PDF (12/18 Pages) Texas Instruments – DS90C032QML LVDS Quad CMOS Differential Line Receiver

Transition Time vs
Power Supply Voltage
Transition Time vs
Ambient Temperature
Typical Application
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FIGURE 5. Point-to-Point Application
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Applications Information
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 5. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100Ω. A termination resistor of
100Ω should be selected to match the media, and is located
as close to the receiver input pins as possible. The termination
resistor converts the current sourced by the driver into a volt-
age that is detected by the receiver. Other configurations are
possible such as a multi-receiver configuration, but the effects
of a mid-stream connector(s), cable stub(s), and other
impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken into
account.
The DS90C032 differential line receiver is capable of detect-
ing signals as low as 100 mV, over a ±1V common-mode
range centered around +1.2V. This is related to the driver off-
set voltage which is typically +1.2V. The driven signal is
centered around this voltage and may shift ±1V around this
center point. The ±1V shifting may be the result of a ground
potential difference between the driver's ground reference
and the receiver's ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. Both
receiver input pins should honor their specified operating in-
put voltage range of 0V to +2.4V (measured from each pin to
ground), exceeding these limits may turn on the ESD protec-
tion circuitry which will clamp the bus voltages.
Receiver Failsafe
The LVDS receiver is a high gain, high speed device that am-
plifies a small differential signal (20mV) to CMOS logic levels.
Due to the high gain and tight threshold of the receiver, care
should be taken to prevent noise from appearing as a valid
signal.
The receiver’s internal failsafe circuitry is designed to source/
sink a small amount of current, providing failsafe protection
(a stable known state of HIGH output voltage) for floating and
terminated (100Ω) receiver inputs in low noise environment
(differential noise < 10mV).
1. Open Input Pins
TheDS90C032 is a quad receiver device, and if an application
requires only 1, 2 or 3 receivers, the unused channel(s) inputs
should be left OPEN. Do not tie unused receiver inputs to
ground or any other voltages. The input is biased by internal
high value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a HIGH,
stable output state for open inputs.
2. Terminated Input
The DS90C032 requires external failsafe biasing for termi-
nated input failsafe.
Terminated input failsafe is the case of a receiver that has a
100Ω termination across its inputs and the driver is in the fol-
lowing situations. Unplugged from the bus, or the driver output
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