DS90C031QML Datasheet, PDF (13/20 Pages) Texas Instruments – DS90C031QML LVDS Quad CMOS Differential Line Driver

Applications Information
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic impedance of
the media is in the range of 100Ω. A termination resistor of
100Ω should be selected to match the media, and is located
as close to the receiver input pins as possible. The termination
resistor converts the current sourced by the driver into a volt-
age that is detected by the receiver. Other configurations are
possible such as a multi-receiver configuration, but the effects
of a mid-stream connector(s), cable stub(s), and other
impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken into
account.
The DS90C031differential line driver is a balanced current
source design. A current mode driver, generally speaking has
a high output impedance and supplies a constant current for
a range of loads (a voltage mode driver on the other hand
supplies a constant voltage for a range of loads). Current is
switched through the load in one direction to produce a logic
state and in the other direction to produce the other logic state.
The typical output current is mere 3.4 mA, a minimum of 2.5
mA, and a maximum of 4.5 mA. The current mode requires
(as discussed above) that a resistive termination be employed
to terminate the signal and to complete the loop as shown in
Figure 6. AC or unterminated configurations are not allowed.
The 3.4 mA loop current will develop a differential voltage of
340 mV across the 100Ω termination resistor which the re-
ceiver detects with a 240 mV minimum differential noise
margin neglecting resistive line losses (driven signal minus
receiver threshold (340 mV – 100 mV = 240 mV)). The signal
is centered around +1.2V (Driver Offset, V_OS) with respect to
ground as shown inFigure 7. Note that the steady-state volt-
age (V_SS) peak-to-peak swing is twice the differential voltage
(V_OD) and is typically 680 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases expo-
nentially in most case between 20 MHz–50 MHz. This is due
to the overlap current that flows between the rails of the device
when the internal gates switch. Whereas the current mode
driver switches a fixed current between its output without any
substantial overlap current. This is similar to some ECL and
PECL devices, but without the heavy static I_CC requirements
of the ECL/PECL designs. LVDS requires > 80% less current
than similar PECL devices. AC specifications for the driver
are a tenfold improvement over other existing RS-422 drivers.
The TRI-STATE function allows the driver outputs to be dis-
abled, thus obtaining an even lower power state when the
transmission of data is not required. The LVDS outputs are
high impedance under power-off condition. This allows for
multiple or redundant drivers to be used in certain applica-
tions.
The footprint of the DS90C031 is the same as the industry
standard 26LS31 Quad Differential (RS-422) Driver.
Pin Descriptions
Pin No. (SOIC)
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
4
12
16
8
FIGURE 7. Driver Output Levels
Name
D_I
D_O+
D_O−
EN
EN*
V_CC
Gnd
Description
Driver input pin, TTL/CMOS compatible
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
Ground pin
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