DS16EV5110A Datasheet, PDF (12/22 Pages) Texas Instruments – DS16EV5110A Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/Sink Applications

FIGURE 3. DS16EV5110A Data Channel
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FIGURE 4. DS16EV5110A Clock Channel
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OUTPUT LEVEL CONTROL
The output amplitude of the TMDS drivers for both the data
channels and the clock channel can be controlled via the SM-
Bus (see Table 1). The default output level is 1000mV p-p.
The following Table presents the output level values support-
ed:
TABLE 5. Output Level Control Settings – REG 0x08[3:2]
Bit 3
Bit 2
Output Level (mV)
0
0
540
0
1
770
1
0
1000 (default)
1
1
1200
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110A to be configured to
automatically enter STANDBY mode if no clock signal is
present. STANDBY mode can be implemented by connecting
the Signal Detect (SD) pin to the external (LVCMOS) Enable
(EN) pin. In order for this option to function properly,
REG07[0] should be set to a “0” (default value). If the clock
signal applied to the clock channel input swings above the
SD_ON threshold specified in the threshold register via the
SMBus, then the SD pin is asserted High. If the SD pin is
connected to the EN pin, this will enable the equalizer, limiting
amplifier, and output buffer on the data channels and the lim-
iting amplifier and output buffer on the clock channel; thus the
DS16EV5110A will automatically enter the ACTIVE state. If
the clock signal present falls below SD_OFF threshold spec-
ified in the threshold register, then the SD pin will be asserted
Low, causing the aforementioned blocks to be placed in the
STANDBY state.
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