DS16EV5110A Datasheet, PDF (11/22 Pages) Texas Instruments – DS16EV5110A Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/Sink Applications

DS16EV5110A Device Description
The DS16EV5110A video equalizer comprises three data
channels, a clock channel, and a control interface including a
Systeml Management Bus (SMBus) port.
DATA CHANNELS
The DS16EV5110A provides three data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a TMDS driver as shown in
Figure 3.
EQUALIZER BOOST CONTROL
The data channel equalizers support eight programmable lev-
els of equalization boost. The state of the FEB pin determines
how the boost settings are controlled. If the FEB pin is held
High, then the equalizer boost setting is controlled by the
Boost Set pins (BST_[0:2]) in accordance with Table 2. If this
programming method is chosen, then the boost setting se-
lected on the Boost Set pins is applied to all three data
channels. When the FEB pin is held Low, the equalizer boost
level is controlled through the SMBus. This programming
method is accessed via the appropriate SMBus registers (see
Table 1). Using this approach, equalizer boost settings can
be programmed for each channel individually. FEB is inter-
nally pulled High (default setting); therefore if left unconnect-
ed, the boost settings are controlled by the Boost Set pins
(BST_[0:2]). The range of boost settings provided enables the
DS16EV5110A to address a wide range of transmission line
path loss scenarios, enabling support for a variety of data
rates and formats.
TABLE 2. EQ Boost Control Table
Control Via
SMBus
BC_2, BC_1,
BC_0
(FEB = 0)
Control Via Pins
BST_2, BST_1,
BST_0
(FEB = 1)
EQ Boost Setting
at 825 MHz (dB)
(TYP)
000
000
9
001
001
14
010
010
18
011
011
21
100
100
24
101
101
26
110
110
28
111
111
30
DEVICE STATE AND ENABLE CONTROL
The DS16EV5110A has an Enable feature which provides the
ability to control device power consumption. This feature can
be controlled either via the Enable Pin (EN Pin) or via the
Enable Control Bit which is accessed through the SMBus port
(see Table 1 and Table 3). If Enable is activated, the data
channels and clock channel are placed in the ACTIVE state
and all device blocks function as described. The
DS16EV5110A can also be placed in STANDBY mode to
save power. In this mode only the control interface including
the SMBus port as well as the clock channel signal detection
circuit remain active.
TABLE 3. Enable and Device State Control
Register 07[0] EN Pin Register 03[3] Device State
(SMBus) (CMOS) (EN Control)
(SMBus)
0 : Disable
1
X
ACTIVE
0 : Disable
0
X
STANDBY
1 : Enable
X
0
ACTIVE
1 : Enable
X
1
STANDBY
CLOCK CHANNEL
The clock channel incorporates a limiting amplifier, a DC off-
set correction, and a TMDS driver as shown in Figure 4.
CLOCK CHANNEL SIGNAL DETECT
The DS16EV5110A features a signal detect circuit on the
clock channel. The status of the clock signal can be deter-
mined by either reading the Signal Detect bit (SD) in the
SMBus registers (see Table 1) or by the state of the SD pin.
A logic High indicates the presence of a signal that has ex-
ceeded a specified threshold value (called SD_ON). A logic
Low means that the clock signal has fallen below a threshold
value (called SD_OFF). These values are programmed via
the SMBus (Table 1). If not programmed via the SMBus, the
thresholds take on the default values for the SD_OFF and
SD_ON values as indicated in Table 4. The Signal Detect
threshold values can be changed through the SMBus. All
threshold values specified are DC peak-to-peak differential
signals (positive signal minus negative signal) at the input of
the device.
TABLE 4. Clock Channel Signal Detect Threshold Values
Bit 1 Bit 0 SD_OFF Threshold SD_ON Threshold
Register 06 (mV) Register 05 (mV)
00
40 (Default)
70 (Default)
01
30
55
10
55
90
11
45
75
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