BUF08630_14 Datasheet, PDF (12/35 Pages) Texas Instruments – Programmable Gamma-Voltage Generator and High Slew Rate VCOM

BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
TWO-WIRE BUS OVERVIEW
The BUF08630 communicates over an industry-
standard, two-wire interface to receive data in slave
mode. This model uses a two-wire, open-drain
interface that supports multiple devices on a single
bus. Bus lines are driven to a logic low level only. The
device that initiates the communication is called a
master, and the devices controlled by the master are
slaves. The master generates the serial clock on the
clock signal line (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line (SDA)
from a high to a low logic level while SCL is high. All
slaves on the bus shift in the slave address byte on
the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
high. Any change in SDA while SCL is high is
interpreted as a START or STOP condition.
Once all data have been transferred, the master
generates a STOP condition, indicated by pulling
SDA from low to high while SCL is high. The
BUF08630 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the
BUF08630.
ADDRESSING THE BUF08630
The address of the BUF08630 is 111010x, where x is
the state of the A0 pin. When the A0 pin is low, the
device acknowledges on address 74h (1110100). If
the A0 pin is high, the device acknowledges on
address 75h (1110101). Table 1 shows the A0 pin
settings and BUF08630 address options.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
www.ti.com
Table 1. Quick Reference of BUF08630 Addresses
DEVICE/COMPONENT
BUF08630 ADDRESS
A0 pin is low
(device acknowledges on address 74h)
A0 pin is high
(device acknowledges on address 75h)
ADDRESS
1110100
1110101
DATA RATES
The two-wire bus operates in one of three speed
modes:
• Standard: allows clock frequency up to 100 kHz;
• Fast: allows clock frequency up to 400 kHz; and
• High-speed mode (also called Hs mode): allows
clock frequency up to 3.4 MHz.
The BUF08630 is fully compatible with all three
modes. No special action is required to use the
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed
mode, send a special address byte of 00001 xxx, with
SCL ≤ 400 kHz, following the START condition;
where xxx are bits unique to the Hs-capable master,
which can be any value. This byte is called the Hs
master code. Table 2 provides a reference for the
High-speed mode command code. (Note that this
configuration is different from normal address
bytes—the low bit does not indicate read/write
status.) The BUF08630 responds to the High-speed
command regardless of the value of these last three
bits. The BUF08630 does not acknowledge this byte;
the
communication
protocol
prohibits
acknowledgment of the Hs master code. Upon
receiving a master code, the BUF08630 switches on
its Hs mode filters, and communicates at up to 3.4
MHz. Additional high-speed transfers may be initiated
without resending the Hs mode byte by generating a
repeat START without a STOP. The BUF08630
switches out of Hs mode with the next STOP
condition.
COMMAND
General-Call Reset
High-Speed Mode
Table 2. Quick Reference of Command Codes
CODE
Address byte of 00h followed by a data byte of 06h.
00001xxx, with SCL ≤ 400 kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
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