AM4376_16 Datasheet, PDF (116/266 Pages) Texas Instruments – Sitara Processors

AM4376, AM4377, AM4378, AM4379
SPRS851C – JUNE 2014 – REVISED APRIL 2016
www.ti.com
Table 5-6. ADC1 Electrical Parameters (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
SAMPLING DYNAMICS
ADC Clock Frequency
13 MHz
Conversion Time
ADC
13
clock
cycles
Acquisition Time⁽⁵⁾
2
Sampling Rate⁽⁶⁾
ADC Clock = 13 MHz
ADC
257 clock
cycles
867 kSPS
(1) The ADC1_VREFP and ADC1_VREFN terminals should not be allowed to float to prevent noise from coupling into the ADC. If
ADC1_VREFN is not used to connect an external negative voltage reference to the ADC, connect it to VSSA_ADC. If ADC1_VREFP is
not used to connect an external positive voltage reference to the ADC, connect it to VSSA_ADC or VDDA_ADC1. Connecting
ADC1_VREFP to VSSA_ADC in this use case is the preferred option because VDDA_ADC1 may couple more noise into the ADC than
VSSA_ADC.
(2) If the application using ADC1 requires low distortion when operating in Gain mode, the preamplifier output should be limited to ±1.2 volts
differential. To get the full dynamic range of the ADC for this use case it will be necessary to provide a 0.3 volt reference for
ADC1_VREFN and 1.5 volt reference for ADC1_VREFP.
(3) The differential input impedance of each preamplifier is biased to VDDA_ADC1 divided by 2 with a 22-kΩ to 50-kΩ source. See the AFE
Functional Description section of the device-specific TRM for more information.
(4) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
(5) The maximum sample rate of ADC1 may be reduced when using the internal preamplifiers because the preamplifier outputs require 600
ns to settle. Sample Delay must be configured to provide a minimum acquisition time of 600 ns when using the preamplifiers.
An increase in acquisition time may reduce the maximum sample rate because the maximum sample rate is based on a minimum
acquisition time of 2 ADC clock cycles.
For example, the minimum Sample Delay value should be 6 when the preamplifiers are being used with a 13-MHz ADC clock. A Sample
Delay of 6 provides an acquisition time of 8 ADC clock cycles, which reduces the maximum single input sample rate to 619 kSPS when
the acquisition time is combined with the conversion time of 13 ADC clock cycles.
(6) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2
ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted
digital value.
116 Specifications
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