TMS570LS2125 Datasheet, PDF (115/154 Pages) Texas Instruments – TMS570LSxxx5 16/32-Bit RISC Flash Microcontroller

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TMS570LS2125
TMS570LS2135
TMS570LS3135
SPNS164 – SEPTEMBER 2011
• Programmable interrupt threshold counter is available for each group
• Programmable magnitude threshold interrupt for each group for any one channel
• Option to read either 8-bit, 10-bit or 12-bit values from memory regions
• Single or continuous conversion modes
• Embedded self-test
• Embedded calibration logic
• Enhanced power-down mode
– Optional feature to automatically power down ADC core when no conversion is in progress
• External event pin (ADEVT) programmable as general-purpose I/O
5.2.2 Event Trigger Options
The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3
groups can be configured to be hardware event-triggered. In that case, the application can select from
among 8 event sources to be the trigger for a group's conversions.
5.2.2.1 Default MIBADC1 Event Trigger Hookup
Event #
1
2
3
4
5
6
7
8
Table 5-3. MIBADC1 Event Trigger Hookup
Source Select Bits For G1, G2 Or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
000
001
010
011
100
101
110
111
Trigger
ADEVT
N2HET1[8]
N2HET1[10]
RTI compare 0 interrupt
N2HET1[12]
N2HET1[14]
GIOB[0]
GIOB[1]
NOTE
For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.2.2.2 Alternate MIBADC1 Event Trigger Hookup
Event #
1
2
Table 5-4. Alternate MIBADC1 Event Trigger Hookup
Source Select Bits for G1, G2 or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
000
001
Trigger
ADEVT
N2HET2[5]
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 115
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