TLC6C5912 Datasheet, PDF (11/23 Pages) Texas Instruments – TLC6C5912 12-Channel Shift-Register LED Driver

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TLC6C5912
SLIS180 – MAY 2016
Feature Description (continued)
8.3.2 Serial-In Interface
The TLC6C598 device contains an 8-bit serial-in, parallel out shift register that feeds an 8-bit D-type storage
register. Data transfer through both the shift and storage registers on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage transfers data to the output buffer when shift
register clear (CLR) is high.
8.3.3 Clear Register
A logic low on CLR clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.4 Cascade Through SER OUT
By connecting the SER OUT pin to the SER IN input of the next device on the serial bus to cascade, the data
transfers to the next device on the falling edge of SRCK. This can improve the cascade application reliability, as
it can avoid that the second device receives SRCK and data input at the same rising edge of SRCK.
8.3.5 Output Control
Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding
G low makes data from the storage register transparent to the output buffers. When data in the output buffers is
low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sink-
current. This pin also be used for global PWM dimming.
8.4 Device Functional Modes
8.4.1 Operation With V_CC < 3 V
This device works normally during 3 V ≤ V_CC ≤ 5.5 V, when operation voltage is lower than 3 V. The behavior of
device cannot be ensured, including communication interface and current capability.
8.4.2 Operation With 5.5 V ≤ V_CC ≤ 8 V
The device works normally during this voltage range, but reliability issues may occurs while the device works for
a long time in this voltage range.
Copyright © 2016, Texas Instruments Incorporated
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