SLOU330 Datasheet, PDF (11/18 Pages) Texas Instruments – EVM Description

www.ti.com
6.2 System Level
Clocking Configuration
In this system configuration on the EVM a VCXO at 6x the
desired clock frequency is required – alternatively a
different VCXO frequency can be used and the internal
CDCE72010 dividers adjusted accordingly. An external
reference can be locked to the VCXO for coherency using
the CDCE72010. In this configuration the CDCE72010
provides a /6 copy of the VCXO to the AFE722x clock
input as well as a /8 copy to the TSW3100.
Also the AFE722x EVM offers a placeholder for a surface
mount bandpass filter between CDCE72010 and
AFE722x to limit the clock phase noise.
Ext
Ref In
E.g. 10 MHZ or
122.88 MHz
CDCE72010
122.88 MHz
/6
6x Fs VCXO
92.16 MHz
/8
737.28MHz
AFE722x
TSW3100
6.3 RX Only
When testing only the ADCs for maximum performance,
the EVM provides an option to connect an external clock
directly to the AFE bypassing the CDCE72010. R74, R76
and R112 need to be modified from their default
configuration.
The DACs of the AFE can still be operated however the
TSW3100 can’t be used for data generation as no
feedback clock is provided to it.
This option provides the lowest possible jitter option when
combined with an external bandpass filter.
AFE722x
VCXO
CDCE72010
6.4 RX and TX Independent Clocking
The AFE722x supports an option to run the dual ADCs at
SMA R112 _R74
Connector 0S _0S
a different sampling rate than the dual DACs. With a few CLK IN
resistor changes, the clocking circuitry on the AFE722x
R76
DNI
EVM can be configured to support that feature. However
in this scenario the CDCE72010 is bypassed and no clock
SMA
R79
Connector
DNI
R161
is routed back to the TSW3100. Hence an additional clock CLK IN\
0S
needs to be provided and the CDCE72010 configured
with the appropriate output divider to match the AFE722x
DAC clock rate with the data rate from the TSW3100 (see
6.1 & 6.2).
0S _R78
0S
R82
50S
T9
C56
0S
DNI
CLK INP
AFE722x
CLK INN
6.5 Interpolation on the DAC
The AFE722x offers 2x and 4x interpolation of the DAC
output data. In order to employ interpolation on the DAC,
the clock going to the TSW3100 needs to be divided
x3
accordingly. For example interpolation by 2x in the DAC ^{AUX IN}
requires that the data coming from the TSW3100 arrives
at ½ of the AFE722x clock frequency.
CDCE72010
/3
Opt. BPF
AFE722x
/8
TSW3100
SLOU330 – December 2011
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
EVM Description
11