LP38512 Datasheet, PDF (11/16 Pages) Texas Instruments – 1.5A Fast-Transient Response Low-Dropout Linear Voltage Regulator with Error Flag

on/off cycling to a lower frequency. Please refer to the POW-
ER DISSIPATION/HEATSINKING section for power dissipa-
tion calculations.
ENABLE OPERATION
The Enable ON threshold is typically 1.2V, and the OFF
threshold is typically 1.0V. To ensure reliable operation the
Enable pin voltage must rise above the maximum V_EN(ON)
threshold and must fall below the minimum V_EN(OFF) thresh-
old. The Enable threshold has typically 200mV of hysteresis
to improve noise immunity.
The Enable pin (EN) has no internal pull-up or pull-down to
establish a default condition and, as a result, this pin must be
terminated either actively or passively.
If the Enable pin is driven from a single ended device (such
as discrete transistor) a pull-up resistor to V_IN, or a pull-down
resistor to ground, will be required for proper operation. A
1 kΩ to 100 kΩ resistor can be used as the pull-up or pull-
down resistor to establish default condition for the EN pin. The
resistor value selected should be appropriate to swamp out
any leakage in the external single ended device, as well as
any stray capacitance.
If the Enable pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator output), the
pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin
should be connected to directly to the adjacent V_IN pin.
The status of the Enable pin also affects the behavior of the
ERROR Flag. While the Enable pin is high the regulator con-
trol loop will be active and the ERROR Flag will report the
status of the output voltage. When the Enable pin is taken low
the regulator control loop is shutdown, the output is turned off,
and the ERROR Flag pin is immediately forced low.
ERROR FLAG OPERATION
When the LP38512 Enable pin is high, the ERROR Flag pin
will produce a logic low signal when the output drops by more
than 15% (typical) from the nominal output voltage. The drop
in output voltage may be due to low input voltage, current
limiting, or thermal limiting. This flag has a built in hysteresis.
The output voltage will need to rise to within 10% (typical) of
the nominal output voltage for the ERROR Flag to return to a
logic high state. It should also be noted that when the Enable
pin is pulled low, the ERROR Flag pin is forced to be low as
well.
The internal ERROR flag comparator has an open drain out-
put stage. Hence, the ERROR pin requires an external
pull-up resistor. The value of the pull-up resistor should be in
the range of 10 kΩ to 1 MΩ. The ERROR Flag pin should not
be pulled-up to any voltage source higher than V_IN as current
flow through an internal parasitic diode may cause unexpect-
ed behavior. The ERROR Flag must be connected to ground
if this function is not used.
The timing diagram in Figure 1 shows the relationship be-
tween the ERROR flag and the output voltage.
FIGURE 1. ERROR Flag Operation, see Typical Application
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