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BQ27750 Datasheet, PDF (11/34 Pages) Texas Instruments – Impedance Track Battery Gas Gauge and Protection Solution for 1-Series Cell Li-Ion Battery Packs
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bq27750
SLUSCM7 – JUNE 2017
N-CH FET Drive (CHG, DSG) (continued)
Typical values stated where TA = 25ºC, Min/Max values stated where TA = –40ºC to 85ºC (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
tF
Fall time
VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between DSG and PACK, 5.1 kΩ between DSG and CL,
10 MΩ between PACK and DSG
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between CHG and BAT, 5.1 kΩ between CHG and CL, 10
MΩ between BAT and CHG
40
300
40
200
UNIT
µs
6.25 I2C Interface I/O
Typical values stated where TA = 25ºC, Min/Max values stated where TA = –40ºC to 85ºC (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN TYP
MAX
VIH
Input voltage high SCL, SDA, VREG = 1.8 V (STANDARD and FAST modes) 0.7 × VREG
VIL
Input voltage low
SCL, SDA, VREG = 1.8 V (STANDARD and FAST modes)
–0.5
SCL, SDA, VREG = 1.8 V, IOL = 3 mA (FAST mode)
VOL
Output low voltage SCL, SDA, VREG > 2.0 V, IOL = 3 mA (STANDARD and
FAST modes)
0.3 × VREG
0.2 × VREG
0.4
CIN
Input capacitance
ILKG
Input leakage
current
10
1
RPD
Pull-down resistance
3.3
UNIT
V
V
V
V
pF
µA
kΩ
6.26 I2C Interface Timing
Typical values stated where TA = 25ºC, Min/Max values stated where TA = –40ºC to 85ºC (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
tR
tF
tHIGH
tLOW
tSU(START)
Clock rise time
10% to 90%
Clock fall time
90% to 10%
Clock high period
Clock low period
Repeated start setup
time
300
300
600
1.3
600
td(START)
Start for first falling
edge to SCL
600
tSU(DATA) Data setup time
100
tHD(DATA) Data hold time
0
tSU(STOP) Stop setup time
600
Bus free time
tBUF
between stop and
1.3
start
fSW
Clock operating
frequency
SLAVE mode, SCL 50% duty cycle
400
UNIT
ns
ns
ns
µs
ns
ns
ns
µs
ns
µs
kHz
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