BQ27750 Datasheet, PDF (10/34 Pages) Texas Instruments – Impedance Track Battery Gas Gauge and Protection Solution for 1-Series Cell Li-Ion Battery Packs

bq27750
SLUSCM7 – JUNE 2017
www.ti.com
Current Protection Thresholds (continued)
Typical values stated where T_A = 25ºC, Min/Max values stated where T_A = –40ºC to 85ºC (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX
ΔV_SCD2
SCD2 detection threshold
voltage program step
V_SCD2 = V_SRP – V_SRN,
PROTECTION_CONTROL[RSNS] = 1
V_SCD2 = V_SRP – V_SRN,
PROTECTION_CONTROL[RSNS] = 0
–22.2
–11.1
UNIT
mV
6.23 Current Protection Timing
Typical values stated where T_A = 25ºC, Min/Max values stated where T_A = –40ºC to 85ºC (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
t_OCD
OCD detection delay
time
1
31
Δt_OCD
OCD detection delay
time program step
2
t_SCC
SCC detection delay
time
0
915
Δt_SCC
SCC detection delay
time program step
61
t_SCD1
SCD1 detection delay ^{PROTECTION_CONTROL[SCDDx2] = 0}
time
PROTECTION_CONTROL[SCDDx2] = 1
0
915
0
1850
Δt_SCD1
SCD1 detection delay ^{PROTECTION_CONTROL[SCDDx2] = 0}
time program step
PROTECTION_CONTROL[SCDDx2] = 1
61
121
t_SCD2
SCD2 detection delay ^{PROTECTION_CONTROL[SCDDx2] = 0}
time
PROTECTION_CONTROL[SCDDx2] = 1
0
458
0
915
Δt_SCD2
SCD2 detection delay ^{PROTECTION_CONTROL[SCDDx2] = 0}
time program step
PROTECTION_CONTROL[SCDDx2] = 1
30.5
61
t_DETECT
t_ACC
Current fault detect
time
Current fault delay time
accuracy
V_SRP – V_SRN = V_T – 3 mV for OCD, SCD1, and SC2,
V_SRP – V_SRN = V_T + 3 mV for SCC
Max delay setting
–10%
160
10%
UNIT
ms
ms
µs
µs
µs
µs
µs
µs
µs
6.24 N-CH FET Drive (CHG, DSG)
Typical values stated where T_A = 25ºC, Min/Max values stated where T_A = –40ºC to 85ºC (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Ratio_DSG = (V_DSG – V_BAT) / V_BAT, 2.2 V < V_BAT < 4.07 V,
10 MΩ between PACK and DSG
Output voltage ratio
Ratio_CHG = (V_CHG – V_BAT) / V_BAT, 2.2 V < V_BAT < 4.07 V,
10 MΩ between BAT and CHG
2.133
2.133
2.333
2.333
2.467
2.467
V_(FETON)
Output voltage,
CHG and DSG on
V_DSG(ON) = V_DSG – V_BAT, 4.07 V ≤ V_BAT ≤ 18 V, 10 MΩ
between PACK and DSG
V_CHG(ON) = V_CHG – V_BAT, 4.07 V ≤ V_BAT ≤ 18 V, 10 MΩ
between BAT and CHG
8.75
9.5
10.25
8.75
9.5
10.25
V_(FETOFF)
t_R
Output voltage,
CHG and DSG off
Rise time
V_DSG(OFF) = V_DSG – V_PACK, 10 MΩ between PACK and
DSG
V_CHG(OFF) = V_CHG – V_BAT, 10 MΩ between BAT and CHG
V_DSG from 0% to 35% V_DSG(ON)(TYP), V_BAT ≥ 2.2 V, C_L =
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and C_L, 10 MΩ between PACK and DSG
V_CHG from 0% to 35% V_CHG(ON)(TYP), V_BAT ≥ 2.2 V, C_L =
4.7 nF between CHG and BAT, 5.1 kΩ between CHG and
C_L, 10 MΩ between BAT and CHG
–0.4
–0.4
0.4
0.4
200
500
200
500
UNIT
—
V
V
µs
10
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