5962-9583401Q2A Datasheet, PDF (11/19 Pages) Texas Instruments – DS90C032QML LVDS Quad CMOS Differential Line Receiver

DS90C032QML
www.ti.com
SNLS203D – MARCH 2006 – REVISED APRIL 2013
TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal quality
reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the amount of
failsafe biasing is now an application design parameter and can be custom tailored for the specific
application. In applications in low noise environments, they may choose to use a very small bias if any. For
applications with less balanced interconnects and/or in high noise environments they may choose to boost
failsafe further. TI's "LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe
biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This
is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and
un-driven states, the common-mode modulation on the bus is held to a minimum.
For additional Failsafe Biasing information, please refer to Application Note AN-1194 (SNLA051) for more
detail.
Pin Descriptions
Pin No. (SOIC)
2, 6, 10, 14
1, 7, 9, 15
3, 5, 11, 13
4
12
16
8
Name
R_I+
R_I−
R_O
EN
EN*
V_CC
Gnd
Description
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
Ground pin
Radiation Environments
Careful consideration should be given to environmental conditions when using a product in a radiation
environment.
Total Ionizing Dose
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level
specified in the Ordering Information table on the front page. Testing and qualification of these products is done
on a wafer level according to MIL-STD-883G, Test Method 1019.7, Condition A and the “Extended room
temperature anneal test” described in section 3.11 for application environment dose rates less than 0.19
rad(Si)/s. Wafer level TID data is available with lot shipments.
Single Event Latch-Up and Functional Interrupt
One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed
according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the
Features on the front page is the maximum LET tested. A test report is available upon request.
Single Event Upset
A report on single event upset (SEU) is available upon request.
Copyright © 2006–2013, Texas Instruments Incorporated
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