LM3S5G56 Datasheet, PDF (1074/1146 Pages) Texas Instruments – Stellaris® LM3S5G56 Microcontroller

Electrical Characteristics
Table 24-3. JTAG Characteristics (continued)
Parameter Parameter Parameter Name
No.
Min Nom
Max
Unit
TCK fall to Data Valid from High-Z, 2-mA drive
23
35
ns
TCK fall to Data Valid from High-Z, 4-mA drive
15
26
ns
J11
T_{TDO_ZDV}
TCK fall to Data Valid from High-Z, 8-mA drive
-
14
25
ns
TCK fall to Data Valid from High-Z, 8-mA drive with
slew rate control
18
29
ns
TCK fall to Data Valid from Data Valid, 2-mA drive
21
35
ns
TCK fall to Data Valid from Data Valid, 4-mA drive
14
25
ns
J12
T_{TDO_DV TCK fall to Data Valid from Data Valid, 8-mA drive} -
13
24
ns
TCK fall to Data Valid from Data Valid, 8-mA drive
with slew rate control
18
28
ns
TCK fall to High-Z from Data Valid, 2-mA drive
9
11
ns
TCK fall to High-Z from Data Valid, 4-mA drive
7
9
ns
J13
T_{TDO_DVZ}
TCK fall to High-Z from Data Valid, 8-mA drive
-
6
8
ns
TCK fall to High-Z from Data Valid, 8-mA drive with
slew rate control
7
9
ns
a. A ratio of at least 8:1 must be kept between the system clock and TCK.
Figure 24-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
Figure 24-3. JTAG Test Access Port (TAP) Timing
TCK
TMS
TDI
TDO
J7
J8
J7
J8
TMS Input Valid
TMS Input Valid
J9
J10
J9
J10
TDI Input Valid
TDI Input Valid
J11
J12
J13
TDO Output Valid
TDO Output Valid
1074
Texas Instruments-Production Data
January 23, 2012