PGA460 Datasheet, PDF (107/114 Pages) Texas Instruments – Ultrasonic Signal Processor and Transducer Driver

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10 Layout
PGA460
SLASEJ4 – APRIL 2017
10.1 Layout Guidelines
A minimum of two layers is required to a accomplish a small-form factor ultrasonic module design. The layers
should be separated by analog and digital signals. The pin map of the device is routed such that the power and
digital signals are on the opposing side of the analog driver and receiver pins. Consider the following best
practices for PGA460 device layout in order of descending priority:
• Separating the grounding types is important to reduce noise at the AFE input of the PGA460. In particular, the
transducer sensor ground, supporting driver, and return-path circuitry should have a separate ground before
being connected to the main ground. Separating the sensor and main grounds through a ferrite bead is best
practice, but not required; a copper-trace or 0-Ω short is also acceptable when bridging grounds.
• The analog return path pins, INP and INN, are most susceptible to noise and therefore should be routed as
short and directly to the transducer as possible. Ensure the INN capacitor is close to the pin to reduce the
length of the ground wire.
• In applications where protection from an ESD strike on the case of the transducer is important, ground routing
of the capacitor on the INN pin should be separate from the device ground and connected directly with the
shortest possible trace to the connector ground.
• The analog drive pins can be high-current, high-voltage, or both and therefore the design limitation of the
OUTA and OUTB pins is based on the copper trace profile. The driver pins are recommended to be as short
and direct as possible when using a transformer, and driving the primary windings with a high-current limit
• The decoupling capacitors for the AVDD, IOREG, and VPWR pins should be placed as close to the pins as
possible
• Any digital communication should be routed away from the analog receiver pins. The IO, TXD, RXD, and
SCLK pins should be routed on the opposite side of the PCB, away from of the analog signals. When the IO
pin is referenced to a high-voltage VPWR, and operating at a high-speed baud rate, the trace to the
connector or master should be as direct as possible
10.2 Layout Example
Legend
Copper Trace - Top
Copper Trace - Bottom
Via
Transducer
Transformer
Sensor Ground
GND 1
INP 2
INN 3
GND 4
OUTA 5
GNDP 6
OUTB 7
IO 8
Charging
Capacitor
100 F
Figure 142. PGA460 Layout Example
To Power Source
Vias to GND
16 AVDD
15 VPWR
14 IOREG
13 DECPL
12 SCLK
11 RXD
To Master
To Master
10 TXD
To Master
9 TEST
To Master
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