RM48L940_15 Datasheet, PDF (101/172 Pages) Texas Instruments – RM48Lx40 16- and 32-Bit RISC Flash Microcontroller

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RM48L940, RM48L740, RM48L540
SPNS175C – APRIL 2012 – REVISED JUNE 2015
Table 6-35. ESM Channel Assignments (continued)
ERROR SOURCES
MibSPI3 - parity
MibADC1 - parity
Reserved
DCAN1 - parity
DCAN3 - parity
DCAN2 - parity
MibSPI5 - parity
Reserved
RAM even bank (B0TCM) - correctable error
CPU - self-test
RAM odd bank (B1TCM) - correctable error
Reserved
DCC1 - error
CCM-R4 - self-test
Reserved
Reserved
Reserved
FMC - correctable error (EEPROM bank access)
FMC - uncorrectable error (EEPROM bank access)
IOMM - Mux configuration error
Power domain controller compare error
Power domain controller self-test error
eFuse Controller Error – this error signal is generated when any bit in the eFuse
controller error status register is set. The application can choose to generate an
interrupt whenever this bit is set to service any eFuse controller error conditions.
eFuse Controller - Self Test Error. This error signal is generated only when a self
test on the eFuse controller generates an error condition. When an ECC self test
error is detected, group 1 channel 40 error signal will also be set.
PLL2 - Slip
Ethernet Controller master interface
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GROUP
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
CHANNELS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
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System Information and Electrical Specifications 101
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