TMS320F28069PZS Datasheet, PDF (100/173 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
www.ti.com
Table 5-29. SPI Master Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}
SPI WHEN (SPIBRR + 1) IS EVEN OR
NO.
SPIBRR = 0 OR 2
MIN
MAX
1 t_c(SPC)M
2 t_w(SPCH)M
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
4t_c(LCO)
0.5t_c(SPC)M – 10
128t_c(LCO)
0.5t_c(SPC)M
t_w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5t_c(SPC)M – 10
0.5t_c(SPC)M
3 t_w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t_c(SPC)M – 10
0.5_tc(SPC)M
t_w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5_tc(SPC)M – 10
0.5t_c(SPC)M
4 t_{d(SPCH-SIMO)M}
Delay time, SPICLK high to SPISIMO
10
valid (clock polarity = 0)
t_{d(SPCL-SIMO)M}
Delay time, SPICLK low to SPISIMO
10
valid (clock polarity = 1)
5 t_{v(SPCL-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5t_c(SPC)M – 10
t_{v(SPCH-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5t_c(SPC)M – 10
8 t_{su(SOMI-SPCL)M}
Setup time, SPISOMI before SPICLK
26
low (clock polarity = 0)
t_{su(SOMI-SPCH)M}
Setup time, SPISOMI before SPICLK
26
high (clock polarity = 1)
9 t_{v(SPCL-SOMI)M}
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25t_c(SPC)M – 10
t_{v(SPCH-SOMI)M}
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
0.25t_c(SPC)M – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) t_c(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
MIN
MAX
5t_c(LCO)
0.5t_c(SPC)M – 0.5t_c(LCO) – 10
127t_c(LCO)
0.5t_c(SPC)M – 0.5t_c(LCO)
0.5t_c(SPC)M – 0.5t_c(LCO) – 10
0.5t_c(SPC)M – 0.5t_c(LCO)
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0.5t_c(SPC)M + 0.5t_c(LCO)
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0.5t_c(SPC)M + 0.5t_c(LCO)
10
10
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
26
26
0.5t_c(SPC)M – 0.5t_c(LCO) – 10
0.5t_c(SPC)M – 0.5t_c(LCO) – 10
UNIT
ns
ns
ns
ns
ns
ns
ns
100 Peripheral and Electrical Specifications
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