MSP430P325A Datasheet, PDF (10/35 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430C32x, MSP430P325A
MIXED SIGNAL MICROCONTROLLER
SLAS219B − MARCH 1999 − REVISED MARCH 2000
oscillator and system clock (continued)
The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:
D High frequency in order to react quickly to system hardware requests or events
D Low frequency in order to minimize current consumption, EMI, etc.
D Stable frequency for timer applications e.g. real time clock (RTC)
D Enable start-stop operation with a minimum of delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency which is multiplied to achieve the desired
nominal operating range:
f_(system) = (N+1) × f_(crystal)
The crystal frequency multiplication is acheived with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO) provides immediate start-up capability together with long term crystal stability. The frequency variation
of the DCO with the FLL inactive is typically 330 ppm which means that with a cycle time of 1 μs the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used which forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal
oscillator.
digital I/O
One 8-bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output
to the application:
D All individual I/O bits are programmable independently.
D Any combination of input, output, and interrupt conditions is possible.
D Interrupt processing of external events is fully implemented for all eight bits of port P0.
D Provides read/write access to all registers with all instructions.
The six registers are:
D Input register
Contains information at the pins
D Output register
Contains output information
D Direction register
Controls direction
D Interrupt flags
Indicates if interrupt(s) are pending
D Interrupt edge select
Contains input signal change necessary for interrupt
D Interrupt enable
Contains interrupt enable pins
All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two
LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three
interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt
event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with the 8-bit Timer/Counter.
10
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443