BQ32002 Datasheet, PDF (10/29 Pages) Texas Instruments – BQ32002 Real-Time Clock (RTC)

BQ32002
SLUSA96B – AUGUST 2010 – REVISED APRIL 2016
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7.4 Device Functional Modes
When the device switches from the main power supply to backup supply, the time-keeping registers [0- 9] cannot
be accessed through the I²C. The access to these registers are only when V_CC > V_REF. The time-keeping
registers can take up to 1 second to update after the device switches from backup power supply to main power
supply.
7.5 Programming
7.5.1 I²C Serial Interface
The I²C interface allows control and monitoring of the RTC by a microcontroller. I²C is a two-wire serial interface
developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1, January 2000).
The bus consists of a data line (SDA) and a clock line (SCL) with off-chip pullup resistors. When the bus is idle,
both SDA and SCL lines are pulled high.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer.
A slave device receives and/or transmits data on the bus under control of the master device. This device
operates only as a slave device.
I²C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while
SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first,
including the data direction bit (R/W). After receiving a valid address byte, this device responds with an
acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. This device
responds to the I²C slave address 11010000b for write commands and slave address 11010001b for read
commands.
This device does not respond to the general call address.
A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W
bit is high, the data from this device are the values read from the register previously selected by a write to the
subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if
complete bytes are received and acknowledged.
A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the
master to terminate the transfer. A master device must wait at least 60 μs after the RTC exits backup mode to
generate a START condition.
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