BQ2050H_15 Datasheet, PDF (10/30 Pages) Texas Instruments – Low-Cost Lithium Ion Power Gauge™ IC

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bq2050H
Table 7. V_OS-Related Current Sense Error
(Current = 1A)
V_OS
Sense Resistor
(µV)
20
50
100
mΩ
50
0.25
0.10
0.05
%
100
0.50
0.20
0.10
%
150
0.75
0.30
0.15
%
180
0.90
0.36
0.18
%
Communicating With the bq2050H
The bq2050H includes a simple single-pin (HDQ plus return)
serial data interface. A host processor uses the interface to
access various bq2050H registers. Battery characteristics
may be easily monitored by adding a single contact to the
battery pack. The open-drain HDQ pin on the bq2050H
should be pulled up by the host system, or may be left float-
ing if the serial interface is not used.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2050H.
The command directs the bq2050H to either store the
next eight bits of data received to a register specified by
the command byte or output the eight bits of data speci-
fied by the command byte. (See Figure 4.)
The communication protocol is asynchronous return-to-
one. Command and data bytes consist of a stream of
eight bits that have a maximum transmission rate of
5K bits/sec. The least-significant bit of a command or
data byte is transmitted first. The protocol is simple
enough that it can be implemented by most host proces-
sors using either polled or interrupt processing. Data in-
put from the bq2050H may be sampled using the pulse--
width capture timers available on some microcontrollers.
should be held for a period, tDH;DV, to allow the host or
bq2050H to sample the data bit.
The final section is used to stop the transmission by re-
turning the HDQ pin to a logic-high state by at least a
period, tSSU;B, after the negative edge used to start com-
munication. The final logic-high state should be until a
period t_CYCH;B, to allow time to ensure that the bit
transmission was stopped properly. The timings for data
and break communication are given in the serial com-
munication timing specification and illustration sec-
tions.
Communication with the bq2050H is always performed
with the least-significant bit being transmitted first. Fig-
ure 5 shows an example of a communication sequence to
read the bq2050H NACH register.
bq2050H Command Code and
Registers
The bq2050H status registers are listed in Table 8 and de-
scribed below. All registers are Read/Write in the bq2050H.
Caution: When writing to bq2050H registers ensure
that proper data is written. A write-verify read is rec-
ommended.
Command Code
The bq2050H latches the command code when eight
valid command bits have been received by the bq2050H.
The command code contains two fields:
I W/R bit
I Command address
The W/R bit of the command code is used to select whether
the received command is for a read or a write function.
The W/R values are:
If a communication error occurs (e.g., t_CYCB > 250µs),
the bq2050H should be sent a BREAK to reinitiate the
serial interface. A BREAK is detected when the HDQ
pin is driven to a logic-low state for a time, t_B or greater.
The HDQ pin should then be returned to its normal
ready-high logic state for a time, t_BR. The bq2050H is
now ready to receive a command from the host proces-
sor.
The return-to-one data bit frame consists of three dis-
tinct sections. The first section is used to start the
transmission by either the host or the bq2050H taking
the HDQ pin to a logic-low state for a period, t_STRH;B.
The next section is the actual data transmission, where
the data should be valid by a period, t_DSU;B, after the
negative edge used to start communication. The data
Command Code Bits
7
65
4
3
2
1
0
W/R -
-
-
-
-
-
-
Where W/R is:
0 The bq2050H outputs the requested register
contents specified by the address portion of com-
mand code.
1 The following eight bits should be written to the
register specified by the address portion of com-
mand code.
The lower seven-bit field of the command code contains
the address portion of the register to be accessed.
10