SN74ALVCH374_16 Datasheet, PDF (1/17 Pages) Texas Instruments – OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH374
OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES118G – JULY 1997 – REVISED OCTOBER 2004
FEATURES
• Operates From 1.65 V to 3.6 V
• Max t_pd of 3.6 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
OE 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V_CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
DESCRIPTION/ORDERING INFORMATION
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
PDIP - N
Tube
SN74ALVCH374N
SOIC - DW
Tube
Tape and reel
SN74ALVCH374DW
SN74ALVCH374DWR
SSOP - DB
Tape and reel
SN74ALVCH374DBR
TSSOP - PW
Tube
Tape and reel
SN74ALVCH374PW
SN74ALVCH374PWR
TVSOP - DGV
Tape and reel
SN74ALVCH374DGVR
TOP-SIDE MARKING
SN74ALVCH374N
ALVCH374
VB374
VB374
VB374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated