SM320DM642-EP_10 Datasheet, PDF (98/170 Pages) Texas Instruments – Video/Imaging Fixed Point Digital Signal Processor

SM320DM642-EP
Video/Imaging Fixed Point Digital Signal Processor
SGUS058C – JUNE 2007 – REVISED JUNE 2009
www.ti.com
AECLKOUTx
ACEx
ABE[7:0]
AEA[22:3]
AED[63:0]
AARE/ASDCAS/ASADS/ASRE ^(C)
1
1
2
3
BE1
BE2
BE3
BE4
4
5
EA1
EA2
EA3
EA4
10
10
11
Q1
Q2
Q3
Q4
8
8
AAOE/ASDRAS/ASOE ^(C)
12
12
AAWE/ASDWE/ASWE ^(C)
A. The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields,
respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and
CEEXT = 0.
B. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
• Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
• Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
• ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the
final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when
ASOE is active (CEEXT = 1).
• Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as
ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect
cycles (RENEN = 1).
• Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
C. AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE,
ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 5-20. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)^{(A) (B)}
98
DM642 Peripheral Information and Electrical Specifications
Submit Documentation Feedback