SM320DM642-EP_10 Datasheet, PDF (152/170 Pages) Texas Instruments – Video/Imaging Fixed Point Digital Signal Processor

SM320DM642-EP
Video/Imaging Fixed Point Digital Signal Processor
SGUS058C – JUNE 2007 – REVISED JUNE 2009
Table 5-70. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
01C8 01E0
01C8 01E4
01C8 01E8
01C8 01EC
01C8 01F0 – 01C8 01FF
01C8 0200 – 01C8 05FF
01C8 0600
01C8 0604
01C8 0608
01C8 060C
01C8 0610
01C8 0614
01C8 0618
01C8 061C
01C8 0620
01C8 0624
01C8 0628
01C8 062C
01C8 0630
01C8 0634
01C8 0638
01C8 063C
01C8 0640
01C8 0644
01C8 0648
01C8 064C
01C8 0650
01C8 0654
01C8 0658
01C8 065C
01C8 0660
01C8 0664
01C8 0668
01C8 066C
01C8 0670
01C8 0674
01C8 0678
01C8 067C
01C8 0680 – 01C8 0FFF
ACRONYM
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
–
(see Table 5-71)
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0INTACK
TX1INTACK
TX2INTACK
TX3INTACK
TX4INTACK
TX5INTACK
TX6INTACK
TX7INTACK
RX0INTACK
RX1INTACK
RX2INTACK
RX3INTACK
RX4INTACK
RX5INTACK
RX6INTACK
RX7INTACK
–
REGISTER NAME
Backoff Test Register
Transmit Pacing Test Register
Receive Pause Timer Register
Transmit Pause Timer Register
Reserved
EMAC Statistics Registers
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Reserved. Do not write.
Transmit Channel 0 Interrupt Acknowledge Register
Transmit Channel 1 Interrupt Acknowledge Register
Transmit Channel 2 Interrupt Acknowledge Register
Transmit Channel 3 Interrupt Acknowledge Register
Transmit Channel 4 Interrupt Acknowledge Register
Transmit Channel 5 Interrupt Acknowledge Register
Transmit Channel 6 Interrupt Acknowledge Register
Transmit Channel 7 Interrupt Acknowledge Register
Receive Channel 0 Interrupt Acknowledge Register
Reserved. Do not write.
Reserved
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152 DM642 Peripheral Information and Electrical Specifications
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