AM3715 Datasheet, PDF (94/280 Pages) Texas Instruments – AM3715/03 Applications Processor

AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
Table 2-5. External Memory Interfaces – GPMC Signals Description⁽¹⁾ (continued)
SIGNAL NAME
[1]
DESCRIPTION [2]
gpmc_d10
GPMC data bit 10 / multiplexed
address gpmc_a11
gpmc_d11
GPMC data bit 11 / multiplexed
address gpmc_a12
gpmc_d12
GPMC data bit 12 / multiplexed
address gpmc_a13
gpmc_d13
GPMC data bit 13 / multiplexed
address gpmc_a14
gpmc_d14
GPMC data bit 14 / multiplexed
address gpmc_a15
gpmc_d15
GPMC data bit 15 / multiplexed
address gpmc_a16
gpmc_ncs0
GPMC Chip Select bit 0
gpmc_ncs1
GPMC Chip Select bit 1
gpmc_ncs2
GPMC Chip Select bit 2
gpmc_ncs3
GPMC Chip Select bit 3
gpmc_ncs4
GPMC Chip Select bit 4
gpmc_ncs5
GPMC Chip Select bit 5
gpmc_ncs6
GPMC Chip Select bit 6
gpmc_ncs7
GPMC Chip Select bit 7
gpmc_io_dir
GPMC IO direction control for use
with external transceivers
gpmc_clk
GPMC clock
gpmc_nadv_ale Address Valid or Address Latch
Enable
gpmc_noe
Output Enable
gpmc_nwe
Write Enable
gpmc_nbe0_cle Lower Byte Enable. Also used for
Command Latch Enable
gpmc_nbe1
Upper Byte Enable
gpmc_nwp
Flash Write Protect
gpmc_wait0
External indication of wait
gpmc_wait1
External indication of wait
gpmc_wait2
External indication of wait
gpmc_wait3
External indication of wait
(1) NA in table stands for "Not Applicable".
TYPE
[3]
IO
BALL
BOTTOM
(CBP
Pkg.) [4]
P1
IO
R1
IO
R2
IO
T2
IO
W1
IO
Y1
O
G4
O
H3
O
V8
O
U8
O
T8
O
R8
O
P8
O
N8
O
N8
O
T4
O
F3
O
G2
O
F4
O
G3
O
U3
O
H1
I
M8
I
L8
I
K8
I
J8
BALL
TOP
(CBP
Pkg.) [5]
AB4
BALL BOTTOM
(CBC Pkg.) [4]
T1
BALL TOP
(CBC Pkg.) [5]
N1
AC4
U2
P2
AB6
U1
P1
AC6
P1
M1
AB7
L2
J2
AC7
M2
K2
Y2
AD8
AA8
Y1
AD1
W1
NA
A3
NA
NA
B6
NA
NA
B4
NA
NA
C4
NA
NA
B5
NA
NA
C5
NA
NA
C5
NA
W2
N1
L1
W1
AD10
AA9
V2
N2
L2
V1
M1
K1
AC12
K2
NA
NA
J1
NA
AB10
AC6
Y5
AB12
AC11
Y10
AC10
AC8
Y8
NA
B3
NA
NA
C6
NA
BALL
BOTTOM
(CUS
Pkg.) [4]
U1
SUBSYSTEM
PIN
MULTIPLEXING
[6]
gpmc_d10
R3
gpmc_d11
T3
gpmc_d12
U2
gpmc_d13
V1
gpmc_d14
V2
gpmc_d15
E2
NA
NA
NA
NA
NA
D2
NA
F4
NA
G5
NA
F3
NA
G4
NA
G4
NA
W2
NA
F1
NA
F2
NA
G3
NA
K5
NA
L1
NA
E1
NA
C1
NA
NA
NA
NA
NA
C2
NA
NOTE
For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem /
SDRC Subsystem Environment section of the AM/DM37x Multimedia Device Technical
Reference Manual (literature number SPRUGN4).
94
TERMINAL DESCRIPTION
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