AM3715 Datasheet, PDF (182/280 Pages) Texas Instruments – AM3715/03 Applications Processor

AM3715, AM3703
SPRS616F – JUNE 2010 – REVISED AUGUST 2011
6.4.2 SDRAM Memory Controller (SDRC)
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NOTE
For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem
section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4).
The SDRAM controller subsystem module provides connectivity between the processor and external
DRAM memory components. The module includes support for double-data-rate SDRAM (mobile DDR).
6.4.2.1 LPDDR Interface
The LPDDR interface is balled out on the bottom side of the CUS package and on the top side of the POP
packages. The LPDDR interface on the top of the POP package has been designed for compatibility any
POP LPDDR device with a matching footprint and compliance with the JEDEC LPDDR-266 specification.
This section provides the timing specification for the bottom-side LPDDR interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory
system without the need for a complex timing closure process. For more information regarding guidelines
for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing
Specification Application Report (literature number SPRAAV0).
6.4.2.1.1 LPDDR Interface Schematic
Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1
x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is
deleted.
182 Timing Requirements and Switching Characteristics
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