TS3L301 Datasheet, PDF (9/16 Pages) Texas Instruments – 16 BIT TO 8 BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON STATE RESISTANCE

TS3L301
16ĆBIT TO 8ĆBIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ONĆSTATE RESISTANCE
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
FOR SKEW
Input Generator
VG1
50 Ω
Input Generator
VG2
50 Ω
VIN
50 Ω
VI
50 Ω
VDD
DUT
TEST CIRCUIT
VO
CL
(see Note A)
2 × VDD
RL
S1
Open
GND
RL
TEST
VDD
S1
RL
VI
CL
V_∆
tsk(o)
3.3 V ± 0.3 V Open
200 Ω VDD or GND 10 pF
tsk(p)
3.3 V ± 0.3 V Open
200 Ω VDD or GND 10 pF
Data In at
Ax or Ay
Data Out at
XB1 or XB2
Data Out at
YB1 or YB2
tPLHx
tsk(o)
tPLHy
tPHLx
3.5 V
2.5 V
1.5 V
VOH
0.5 V (VOH − VOL) _Input
VOL
tsk(o)
VOH
0.5 V (VOH − VOL)
VOL
tPHLy
Output
3.5 V
2.5 V
1.5 V
tPLH
tPHL
VOH
0.5 V (VOH − VOL)
VOL
tsk(p) = |tPLH − tPLH|
tsk(o) = |tPLHy − tPLHx| or |tPHLy − TPHLx|
VOLTAGE WAVEFORMS
OUTPUT SKEW (tsk(o))
VOLTAGE WAVEFORMS
PULSE SKEW (tsk(p))
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 5. Test Circuit and Voltage Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9