TS3L301 Datasheet, PDF (8/16 Pages) Texas Instruments – 16 BIT TO 8 BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON STATE RESISTANCE

TS3L301
16ĆBIT TO 8ĆBIT SPDT GIGABIT LAN SWITCH
WITH LOW AND FLAT ONĆSTATE RESISTANCE
SCDS178B − NOVEMBER 2004 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
FOR ENABLE AND DISABLE TIMES
Input Generator
VG1
50 Ω
Input Generator
VG2
50 Ω
VIN
50 Ω
VI
50 Ω
VDD
DUT
TEST CIRCUIT
VO
CL
(see Note A)
2 × VDD
RL
S1
Open
GND
RL
TEST
tPLZ/tPZL
tPHZ/tPZH
VDD
3.3 V ± 0.3 V
3.3 V ± 0.3 V
S1
2 × VDD
GND
RL
200 Ω
200 Ω
VI
GND
VDD
CL
10 pF
10 pF
V_∆
0.3 V
0.3 V
Output Control
(VIN)
Output
Waveform 1
S1 at 2 y VDD ^tPZL
(see Note B)
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
1.25 V
VDD/2
VDD/2
1.25 V
tPLZ
2.5 V
0V
VOH
VOL +0.3 V _VOL
tPHZ
VOH −0.3 V ^VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 4. Test Circuit and Voltage Waveforms
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