TCA9535 Datasheet, PDF (9/32 Pages) Texas Instruments – LOW VOLTAGE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

TCA9535
www.ti.com........................................................................................................................................... SCPS201A – AUGUST 2009 – REVISED SEPTEMBER 2009
CONTROL REGISTER BITS
B2
B1
B0
1
1
1
Control Register (continued)
COMMAND
BYTE (HEX)
REGISTER
0x07
Configuration Port 1
PROTOCOL
Read/write
byte
POWER-UP
DEFAULT
1111 1111
Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration Register. It only acts on read operation. Writes to
these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I²C device know that the
Input Port registers will be accessed next.
Bit
Default
Bit
Default
Registers 0 and 1 (Input Port Registers)
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
X
X
X
X
X
X
X
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Bit
Default
Bit
Default
Registers 2 and 3 (Output Port Registers)
O0.7
1
O1.7
1
O0.6
1
O1.6
1
O0.5
1
O1.5
1
O0.4
1
O1.4
1
O0.3
1
O1.3
1
O0.2
1
O1.2
1
O0.1
1
O1.1
1
O0.0
1
O1.0
1
The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in this register is set (written with 1), the corresponding pin's polarity is inverted. If a
bit in this register is cleared (written with a 0), the corresponding pin's original polarity is retained.
Bit
Default
Bit
Default
Registers 4 and 5 (Polarity Inversion Registers)
N0.7
0
N1.7
0
N0.6
0
N1.6
0
N0.5
0
N1.5
0
N0.4
0
N1.4
0
N0.3
0
N1.3
0
N0.2
0
N1.2
0
N0.1
0
N1.1
0
N0.0
0
N1.0
0
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this
register is cleared to 0, the corresponding port pin is enabled as an output.
Bit
Default
Bit
Default
Registers 6 and 7 (Configuration Registers)
C0.7
1
C1.7
1
C0.6
1
C1.6
1
C0.5
1
C1.5
1
C0.4
1
C1.4
1
C0.3
1
C1.3
1
C0.2
1
C1.2
1
C0.1
1
C1.1
1
C0.0
1
C1.0
1
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