TCA9535 Datasheet, PDF (12/32 Pages) Texas Instruments – LOW VOLTAGE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

TCA9535
SCPS201A – AUGUST 2009 – REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com
SCL
1 23 4 567 89
I0.x
I1.x
I0.x
I1.x
SDA S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P
Read From Port 0
R/W _Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
t_iv
t_ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
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SCL
12345678 9
I0.x
SDA S 0 1 0 0 A2 A1 A0 1 A
00
Acknowledge
R/W From Slave
t_ph
Read From Port 0
A
Acknowledge
From Master
I1.x
10
A
Acknowledge
From Master
t_ps
I0.x
03
A
Acknowledge
From Master
I1.x
12
1P
No Acknowledge
From Master
Data Into Port 0
Read From Port 1
Data Into Port 1
Data 00
Data 01
Data 10
Data 02
t_ph
Data 11
Data 03
t_ps
Data 12
INT
t_iv
t_ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8 for these details).
Figure 10. Read Input Port Register, Scenario 2
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