SN74FB1653 Datasheet, PDF (9/12 Pages) Texas Instruments – 17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER WITH BUFFERED CLOCK LINE

From Output
Under Test
CL = 50 pF
(see Note A)
SN74FB1653
17ĆBIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
2.1 V
500 Ω
500 Ω
6V
S1
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
16.5 Ω
Test
Point
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6V
GND
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
Input
tw
3V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
1.5 V
tPHL
1.5 V
3V
0V
tPLH
Timing Input
Data Input
3V
1.5 V
0V
tsu
th
1.5 V
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.55 V
VOH
1.55 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A to B)
Input
1.55 V
2V
1.55 V
1V
tPHL
tPLH
Output
1.5 V
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
Output
Control
(see Note B)
1.5 V
3V
1.5 V
0V
tPZL
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
tPLZ
3V
VOL + 0.3 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
tPZH
1.5 V
tPHZ
VOH
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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