DRV110 Datasheet, PDF (9/17 Pages) Texas Instruments – POWER SAVING SOLENOID CONTROLLER WITH INTEGRATED SUPPLY REGULATION

DRV110
www.ti.com
SLVSBA8 – MARCH 2012
Frequency of the internal PWM clock signal, PWM_CLK, that triggers each OUT pin ON-cycle can be adjusted by
external resistor, R_OSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 5. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of
external fixed adjustment resistor value (greater than 66.67 kΩ) is given below.
60kHz
f_PWM = _ROSC × 66.67kW;66.67kW < R_OSC < 2MW
(4)
Figure 5. PWM Clock Frequency Setting
Voltage at the OUT pin, that is the gate voltage of an external switching device, is equal to VIN voltage during
ON-cycle. It is driven to ground during OFF-cycle. VIN voltages below 15 V can be supplied directly from an
external voltage source. Supply voltages of at least 6 V are supported.
DRV110 is able to regulate VIN voltage to 15 V from a higher external supply voltage, V_S, by an internal bypass
regulator that replicates the function of an ideal Zener diode. This requires that the supply current is sufficiently
limited by an external resistor between V_S and the VIN pin. An external capacitor connected to the VIN pin is
used to store enough energy to charge the external switch gate capacitance at the OUT pin. Current limiting
resistor size to keep quiescent current less than 1 mA can be calculated by Equation 5.
R_S
=
V_S,maxDC - 15V
1mA + I_Gate,AVE
(5)
Open-drain pull-down path at the STATUS pin is deactivated if either under voltage lockout or thermal shutdown
blocks have triggered.
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DRV110
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