DRV110 Datasheet, PDF (7/17 Pages) Texas Instruments – POWER SAVING SOLENOID CONTROLLER WITH INTEGRATED SUPPLY REGULATION

DRV110
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FUNCTIONAL DESCRIPTION
SLVSBA8 – MARCH 2012
DRV110 controls the current through the solenoid as shown in Figure 3. Activation starts when EN pin voltage is
pulled high either by an external driver or internal pull-up. In the beginning of activation, DRV110 allows the load
current to ramp up to the peak value I_PEAK and it regulates it at the peak value for the time, t_KEEP, before reducing
it to I_HOLD. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current
ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV110
allows the solenoid current to decay to zero.
I_SOLENOID
I_PEAK
I_HOLD
t
t_KEEP
EN
t
Figure 3. Typical Current Waveform Through the Solenoid
t_KEEP is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP
pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage
reaches 100 mV, the current regulation reference voltage, V_REF, is switched from V_PEAK to V_HOLD. Dependency of
t_KEEP from the external capacitor size can be calculated by:
t_KEEP
éësùû
=
C_KEEP
éëFùû
× 10⁵
és
êë _F
ù
úû
(1)
The current control loop regulates, cycle-by-cycle, the solenoid current by sensing voltage at the SENSE pin and
controlling the external switching device gate through the OUT pin. During the ON-cycle, the OUT pin voltage is
driven and kept high (equal to VIN voltage) as long as the voltage at the SENSE pin is less than V_REF allowing
current to flow through the external switch. As soon as the voltage at the SENSE pin is above V_REF, the OUT pin
voltage is immediately driven and kept low until the next ON-cycle is triggered by the internal PWM clock signal.
In the beginning of each ON-cycle, the OUT pin voltage is driven and kept high for at least the time determined
by the minimum PWM signal duty cycle, D_MIN.
V_PEAK and V_HOLD depend on fixed resistance values R_PEAK and R_HOLD as shown in Figure 4. If the PEAK pin is
connected to ground, the peak current reference voltage, V_PEAK, is at it’s default value (internal setting). The
V_PEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For
example, if a 50-kΩ (= R_PEAK) resistor is connected between PEAK and GND, and R_SENSE = 1 Ω, then the
externally set I_PEAK level will be 900 mA. If R_PEAK = 200 kΩ and R_SENSE = 1 Ω, then the externally set I_PEAK level
will be 300 mA. In case R_SENSE = 2 Ω instead of 1 Ω, then I_PEAK = 450 mA (when R_PEAK = 50 kΩ) and
I_PEAK = 150 mA (when R_PEAK = 200 kΩ). External setting of the HOLD current, I_HOLD, works in the same way, but
the current levels are 1/6 of the I_PEAK levels. External settings for I_PEAK and I_HOLD are independent of each other.
If R_PEAK is decreased below 33.33 kΩ (typ value), then the reference is clamped to the internal setting. The same
is valid for R_HOLD and I_HOLD. I_PEAK and I_HOLD values can be calculated by using the formula below.
I_PEAK
=
1W
R_SENSE
900mA
×
R_PEAK
× 66.67kW;66.67kW
< R_PEAK
< 2MW
(2)
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DRV110
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