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| CD54HCT161 Datasheet, PDF (9/16 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Counters | |||
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Timing Diagram
MASTER RESET (161)
MASTER RESET (163)
SPE
P0
PRESET P1
DATA
INPUTS P2
P3
CP (161)
CP (163)
PE
COUNT
ENABLES
TE
Q0
Q1
OUTPUTS
Q2
Q3
TC
(ASYNCHRONOUS)
(SYNCHRONOUS)
12 13 14 15
012
RESET PRESET
COUNT
INHIBIT
Sequence illustrated on waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, ï¬fteen, zero, one, and two.
4. Inhibit.
9
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