CD54HCT161 Datasheet, PDF (3/16 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Counters

CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
OPERATING MODE
Reset (Clear)
Parallel Load
Count
Inhibit
MODE SELECT - FUNCTION TABLE FOR ’HC161 AND ’HCT161
INPUTS
MR
CP
PE
TE
SPE
P_n
L
X
X
X
X
X
H
↑
X
X
l
l
H
↑
X
X
l
h
H
↑
h
h
h (Note 3)
X
H
X
I (Note 2)
X
h (Note 3)
X
H
X
X
I (Note 2) h (Note 3)
X
OUTPUTS
Q_n
TC
L
L
L
L
H
(Note 1)
Count
(Note 1)
q_n
(Note 1)
q_n
L
MODE SELECT - FUNCTION TABLE FOR ’HC163 AND ’HCT163
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
PE
TE
SPE
P_n
Q_n
TC
Reset (Clear)
l
↑
X
X
X
X
L
L
Parallel Load
h (Note 3)
↑
X
X
l
l
L
L
h (Note 3)
↑
X
X
l
h
H
(Note 1)
Count
h (Note 3)
↑
h
h
h (Note 3)
X
Count
(Note 1)
Inhibit
h (Note 3)
X
I (Note 2)
X
h (Note 3)
X
q_n
(Note 1)
h (Note 3)
X
X
I (Note 2) h (Note 3)
X
q_n
L
H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock
transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate the
state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and ’HC/HCT163).
2. The High-to-Low transition of PE or TE on the ’HC/HCT161 and the ’HC/HCT163 should only occur while CP is HIGH for conventional
operation.
3. The Low-to-High transition of SPE on the ’HC/HCT161 and SPE or MR on the ’HC/HCT163 should only occur while CP is HIGH for
conventional operation.
3