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CD54HCT161 Datasheet, PDF (8/16 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Counters
◁
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued)
PARAMETER
MR to Qn (161)
TEST
SYMBOL CONDITIONS VCC (V) MIN
tPHL
CL = 50pF
2
-
4.5
-
25oC
TYP MAX
- 210
-
42
-40oC TO
85oC
MIN MAX
-
265
-
53
-55oC TO
125oC
MIN MAX UNITS
-
315 ns
-
63
ns
MR to TC (161)
tPHL
CL = 15pF
5
CL = 50pF
6
CL = 50pF
2
4.5
-
18
-
-
-
-
-
-
36
-
45
-
-
-
210
-
265
-
-
-
42
-
53
-
-
ns
54
ns
315 ns
63
ns
Output Transition Time
CL = 50pF
6
-
-
36
-
45
-
54
ns
tTHL, tTLH CL = 50pF
2
-
-
75
-
95
-
110 ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Power Dissipation Capacitance CPD
-
(Notes 7, 8)
5
-
60
-
-
-
-
-
pF
Input Capacitance
HCT TYPES
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
Propagation Delay
CP to TC
tPHL, tPLH CL = 50pF
4.5
-
-
42
-
53
-
63
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
CP to Qn
tPHL, tPLH CL = 50pF
4.5
-
-
39
-
49
-
59
ns
CL = 15pF
5
-
16
-
-
-
-
-
ns
TE to TC
tPHL, tPLH CL = 50pF
4.5
-
-
32
-
40
-
48
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
MR to Qn (161)
tPHL
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
MR to TC (161)
tPHL
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
Output Transition Time
tTHL, tTLH CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Power Dissipation Capacitance CPD
-
(Notes 7, 8)
5
-
63
-
-
-
-
-
pF
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
NOTES:
7. CPD is used to determine the dynamic power consumption, per package.
8. PD = CPD VCC2 fi + ∑(CL VCC2 fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
8
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