BQ2013H Datasheet, PDF (9/24 Pages) Texas Instruments – Gas Gauge IC for Power- Assist Applications

bq2013H
Self-Discharge Compensation
The self-discharge compensation can be programmed for
three different rates. The rates vary across 8 ranges
from <10°C to >70°C, doubling with each higher tem-
perature step (10°C). See Table 7.
Table 7. Self-Discharge Compensation
Temperature
Range
Self-Discharge Compensation
Typical Rate/Day
PROG₃ = H PROG₃ = Z PROG₃ = L
< 10°C
NAC
256
NAC
512
NAC
2048
10–20°C
NAC
128
NAC
256
NAC
1024
20–30°C
NAC
64
NAC
128
NAC
512
30–40°C
NAC
32
NAC
64
NAC
256
40–50°C
NAC
16
NAC
32
NAC
128
50–60°C
NAC
8
NAC
16
NAC
64
60–70°C
NAC
4
NAC
8
NAC
32
> 70°C
NAC
2
NAC
4
NAC
16
Offset Compensation
The bq2013H uses a voltage to frequency converter to
measure the voltage across a resistor used to monitor
the current into and out of the battery. This converter
has an offset value that can be influenced by the V_CC
supply and the bypassing of this supply. The typical
value found on a well designed PCB is about -75µV. Pro-
gram pin 6 can be used to compensate for this offset, re-
ducing the effective V_OS. Offset compensation occurs
when V_SRO < -250µV or V_SRO > 250µV.
Error Summary
The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value includes
the error between the programmed full capacity and the
actual capacity. This error is present until a valid dis-
charge occurs and LMD is updated (see the DCR de-
scription in the “Layout Considerations” section). The
other cause of LMD error is battery wear-out. As the
battery ages, the measured capacity must be adjusted to
account for changes in actual battery capacity.
DONE Input
A fast-charge controller IC or micro-controller uses the
DONE input to communicate charge status to the
bq2013H. When the DONE input is asserted high on
fast-charge completion, the bq2013H sets NAC = LMD
and VDQ = 1. The DONE input should be maintained
high as long as the fast-charge controller or
microcontroller keeps the batteries full; otherwise the
pin should be held low.
Communicating With the bq2013
The bq2013H includes a simple single-pin (HDQ plus re-
turn) serial data interface. A host processor uses the inter-
face to access various bq2013H registers. Battery character-
istics may be easily monitored by adding a single contact to
the battery pack. The open-drain HDQ pin on the bq2013H
should be pulled up by the host system, or may be left float-
ing if the serial interface is not used.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2013H.
The command directs the bq2013H to either store the
next eight bits of data received to a register specified by
the command byte or output the eight bits of data speci-
fied by the command byte. (See Figure 3.)
The communication protocol is asynchronous re-
turn-to-one. Command and data bytes consist of a
stream of eight bits that have a maximum transmission
rate of 5K bits/s. The least-significant bit of a command
or data byte is transmitted first. The protocol is simple
enough that it can be implemented by most host proces-
sors using either polled or interrupt processing. Data
input from the bq2013H may be sampled using the
pulse-width capture timers available on some microcon-
trollers.
If a communication error occurs, e.g., t_CYCB > 250µs, the
bq2013H should be sent a BREAK to reinitiate the se-
rial interface. A BREAK is detected when the HDQ pin
is driven to a logic-low state for a time, t_B or greater.
The HDQ pin should then be returned to its normal
ready-high logic state for a time, t_BR. The bq2013H is
now ready to receive a command from the host proces-
sor.
The return-to-one data bit frame consists of three dis-
tinct sections. The first section is used to start the trans-
mission by either the host or the bq2013H taking the
HDQ pin to a logic-low state for a period, t_STRH;B. The
next section is the actual data transmission, where the
data should be valid by a period, t_DSU;B, after the nega-
tive edge used to start communication. The data should
be held for a period, t_DH;DV, to allow the host or bq2013H
to sample the data bit.
The final section is used to stop the transmission by re-
turning the HDQ pin to a logic-high state by at least a
period, t_SSU;B, after the negative edge used to start com-
munication. The final logic-high state should be until a
period t_CYCH;B, to allow time to ensure that the bit
transmission was stopped properly. The timings for data
and break communication are given in the serial com-
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