ADS54T01_15 Datasheet, PDF (9/47 Pages) Texas Instruments – Single 12-Bit 750Msps Receiver and Feedback IC

ADS54T01
www.ti.com
SLAS918A – DECEMBER 2012 – REVISED JANUARY 2014
ELECTRICAL CHARACTERISTICS
Typical values at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 500Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
OVER-DRIVE RECOVERY ERROR
Input overload recovery
Recovery to within 5% (of final value) for 6dB
overload with sine wave input
2
ns
SAMPLE TIMING CHARACTERISTICS
rms Aperture Jitter
Sample uncertainty
100
fs rms
Data Latency
ADC sample to digital output, Auto correction
disabled
ADC sample to digital output, Auto correction
enabled
38
Clock
Cycles
50
ADC sample to digital output, Decimation filter
enabled, Auto correction disabled
Sampling
74
clock
Cycles
Over-range Latency
ADC sample to over-range output
12
Clock
Cycles
ELECTRICAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE
High-level input voltage
Low-level input voltage
All digital inputs support 1.8V and 3.3V logic
levels.
0.7 x
IOVDD
V
0.3 x
IOVDD
V
High-level input current
–50
200 µA
Low-level input current
–50
50 µA
Input capacitance
5
pF
DIGITAL OUTPUTS – SDO
High-level output voltage
Iload = -100uA
Iload = -2mA
IOVDD –
0.2
V
0.8 x
IOVDD
Low-level output voltage
Iload = 100uA
Iload = 2mA
0.2
0.22 x
V
IOVDD
DIGITAL INPUTS – SYNCP/N, TRIGGERP/N
V_ID Differential input voltage
250
V_CM Input common mode voltage
1.125
t_SU
500
DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N
350
450 mV
1.2
1.375 V
ps
V_OD
V_OCM
t_su
Output differential voltage
Output common mode voltage
F_s = 750Msps
t_h
F_s = 750Msps
Iout = 3.5mA
Iout = 3.5mA
Data valid to zero-crossing of DACLK
Zero-crossing of DACLK to data becoming
invalid
250
1.125
320
250
350
450 mV
1.25
1.375 V
400
ps
320
ps
t_PD
t_RISE
t_FALL
F_s = 750Msps
CLKIN falling edge to DACLK rising edge
10% - 90%
90% - 10%
3.36
3.69
3.92 ns
100
150
200 ps
100
150
200 ps
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