ADS54T01_15 Datasheet, PDF (25/47 Pages) Texas Instruments – Single 12-Bit 750Msps Receiver and Feedback IC

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ADS54T01
SLAS918A – DECEMBER 2012 – REVISED JANUARY 2014
Manual Trigger Mode
The control of the high resolution output is shown below along with the two output flags (TRDY and HRES).
Enable
Burst Mode
Manual Trigger
TRIGGER
Trigger on rising
edge of TRIGGER
tTRIG_DELAY
TRDY
DA[11..0]
Low Resolution
2¹³ samples
High-Resolution
2¹⁰ samples
Ready for
new trigger
Update value N
Low Resolution
2^(N+3) samples
High-Resolution
2^N samples
Ready for
new trigger
HRES
Figure 38. Triggering High Resolution Mode and Lockout Time
After enabling burst mode, the output data DA[11..0] are forced to low resolution mode for 2¹³ samples. During
that period any trigger signal is ignored. The completion of the low resolution sample cycle is signaled by a logic
high on the TRDY output pins indicating that a high resolution (12-bit) data output burst can be triggered by a low
to high transition on the TRIGGER input. The ADC monitors the TRIGGER input at each rising edge of the input
clock.
The high resolution output data starts with a delay of t_{TRIG_DELAY} = 1-2 DACLK clock cycles and is indicated
through the HRES data flag which stays high for all 2^N high resolution samples. At completion the register value
for N is verified and transmission of 2^(N+3) low resolution data immediately follows. Once the last low resolution
sample is output on the output data bus, the flag TRDY is asserted high again indicating the end of the lockout
period and the next 2^N high resolution samples can be triggered again.
Auto Trigger Mode
This mode is enabled by setting the auto trigger bit via SPI register write and the DA data outputs start in low
resolution for 2¹³ samples. Immediately following completion of transmission of the last low resolution sample,
the outputs automatically start transmitting 2¹⁰ high resolution samples without the need for external trigger
ensuring maximum efficiency. Any input signal on the TRIGGER pins is ignored and the TRDY flag will go high
only for one clock cycle with the start of the high resolution data.
The output flag HRES is aligned with the 2^N high resolution output samples and the parameter N can be changed
until the next output cycle starts again with low resolution output data.
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