XIO2000A Datasheet, PDF (89/155 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge

Classic PCI Configuration Space
4.63 Control and Diagnostic Register 2
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−37 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset:
Register type:
Default value:
C8h
Read/Write
3214 6000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−37. Control and Diagnostic Register 2 Description
BIT FIELD NAME ACCESS
DESCRIPTION
31:24†
N_FTS_
ASYNC_CLK
N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see
RW Section 4.53) is clear, the value in this field is the number of FTS that are sent on a transition from
L0s to L0. This field shall default to 32h.
23:16†
N_FTS_
COMMON_
CLK
N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section
RW 4.53) is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0.
This field defaults to 14h.
15:13
PHY_REV
R
PHY revision number
12:8† LINK_NUM
RW Link number
7:6
RSVD
R
Reserved. Returns 00b when read.
5:0
BAROWE
BAR 0 Write Enable. When this bit is clear (default), the Base Address at offset 10h is read only
RW
and writes to that register will have no effect. When this bit is set, then bits 31:12 of the Base
Address Register becomes writeable allowing the address of the 4K window to the Memory
Mapped TI Proprietary Registers to be changed.
4:0†
RSVD
RW
Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00000b.
† _{These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.}
4.64 Subsystem Access Register
The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 84h and 86h. See Table 4−38 for a complete description of the register contents.
PCI register offset:
Register type:
Default value:
D0h
Read/Write
0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−38. Subsystem Access Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:16†
SubsystemID
RW
Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI
offset 86h (see Section 4.45).
15:0† SubsystemVendorID
RW
Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 84h (see Section 4.44).
† _{These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.}
April 2007
SCPS155B
79