XIO2000A Datasheet, PDF (58/155 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge

Classic PCI Configuration Space
4.4 Status Register
The status register provides information about the PCI Express interface to the system. See Table 4−3 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
06h
Read-only, Read/Clear
0010h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Table 4−3. Status Register Description
BIT FIELD NAME ACCESS
DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP. This
bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h, see
15
PAR_ERR
RCU ^{Section 4.3).}
0 = No parity error detected
1 = Parity error detected
Signaled system error. This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL
message and bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set.
14
SYS_ERR
RCU
0 = No error signaled
1 = ERR_FATAL or ERR_NONFATAL signaled
Received master abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-unsupported-request status.
13
MABORT
RCU
0 = Unsupported request not received on the PCI Express interface
1 = Unsupported request received on the PCI Express interface
Received target abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-completer-abort status.
12 TABORT_REC RCU
0 = Completer abort not received on the PCI Express interface
1 = Completer abort received on the PCI Express interface
Signaled target abort. This bit is set when the PCI Express interface completes a request with
completer abort status.
11
TABORT_SIG
RCU
0 = Completer abort not signaled on the PCI Express interface
1 = Completer abort signaled on the PCI Express interface
10:9 PCI_SPEED
R
DEVSEL timing. These bits are read-only 00b, because they do not apply to PCI Express.
Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset 04h,
see Section 4.3) is set and the bridge receives a completion with data marked as poisoned on the
8
DATAPAR
RCU ^{PCI Express interface or poisons a write request received on the PCI Express interface.}
0 = No uncorrectable data error detected on the primary interface
1 = Uncorrectable data error detected on the primary interface
7
FBB_CAP
R
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device
and is hardwired to 0b.
6
RSVD
R
Reserved. Returns 0b when read.
5
66MHZ
R
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to 0b.
4
CAPLIST
Capabilities list. This bit returns 1b when read, indicating that the bridge supports additional PCI
R
capabilities.
3
INT_STATUS
R
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b since
the bridge does not generate any interrupts internally.
2:0
RSVD
R
Reserved. Returns 000b when read.
48 SCPS155B
April 2007