XIO2000A Datasheet, PDF (128/155 Pages) Texas Instruments – PCI Express to PCI Bus Translation Bridge

Memory-Mapped TI Proprietary Register Space
6.8 Upstream Isochronous Window 1 Control Register
The upstream isochronous window 1 control register allows software to identify the TC associated with
upstream transactions targeting memory addresses in the range defined by the window. See Table 6−5 for
a complete description of the register contents.
Device control memory window register offset:
Register type:
Default value:
14h
Read-only, Read/Write
0000h
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6−5. Upstream Isochronous Window 1 Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
3:1
TC_ID
RW
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
Isochronous window enable.
0
ISOC_WINDOW_EN
RW
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are
applied to the appropriate TC
6.9 Upstream Isochronous Window 1 Base Address Register
The upstream isochronous window 1 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
18h
Read/Write
0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6.10 Upstream Isochronous Window 1 Limit Register
The upstream isochronous window 1 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Device control memory window register offset:
Register type:
Default value:
1Ch
Read/Write
0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RESET STATE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
118 SCPS155B
April 2007