TMS320F243 Datasheet, PDF (89/116 Pages) Texas Instruments – DSP CONTROLLERS

SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
1
2
3
6
7
Master Out Data Is Valid
10
11
Master In Data
Must Be Valid
Data Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until}
the SPI communication stream is complete.
Figure 35. SPI Master Mode External Timing (Clock Phase = 1)
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