TMS320F243 Datasheet, PDF (10/116 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
Terminal Functions - ’F243 PGE Package (Continued)
NAME
144
QFP
NO.
TYPE†
RESET
STATE‡
DESCRIPTION
INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS (CONTINUED)
PMT
68
I
I
Enables parallel module test (PMT). Do not connect, reserved for test.
VCCP/WDDIS
Flash programming voltage pin and watchdog disable. This is the 5-V supply used
77
I
I
for flash programming. Flash cannot be programmed if this pin is held at 0 V. This
pin also works as a hardware watchdog disable, when VCCP/WDDIS = +5 V and
bit 6 in WDCR is set to 1.
DEDICATED I/O SIGNALS
IOPD2
20
I/O
Dedicated GPIO – Port D bit 2
IOPD3
21
I/O
Dedicated GPIO – Port D bit 3
IOPD4
IOPD5
23
I/O
Dedicated GPIO – Port D bit 4
I
25
I/O
Dedicated GPIO – Port D bit 5
IOPD6
27
I/O
Dedicated GPIO – Port D bit 6
IOPD7
29
I/O
Dedicated GPIO – Port D bit 7
DATA AND ADDRESS BUS SIGNALS
D0
33
D1
35
D2
38
D3
46
D4
48
D5
50
D6
52
D7
54
I/O/Z
O¶ Bit x of the 16-bit Data Bus
D8
57
D9
59
D10
61
D11
63
D12
65
D13
67
D14
69
D15
71
† _{I = input, O = output, Z = high impedance}
‡ _{The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is}
an output, its level at reset is indicated.
§ _{In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.}
¶ _{Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS}
is enabled.
NOTE: Bold, italicized pin names indicate pin function after reset.
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