SM320DM6446-HIREL_15 Datasheet, PDF (88/228 Pages) Texas Instruments – Digital Media System-on-Chip

SM320DM6446
Digital Media System-on-Chip
SPRS607A – JUNE 2009 – REVISED JUNE 2009
www.ti.com
Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see Figure 6-4)
NO.
MIN MAX UNIT
1 t_{d(CVDD-CVDDDSP)} Delay time, CV_DD supply ready to CV_DDDSP supply ramp start
0
(1)
ns
(1) In Host-Boot mode, the CV_DDDSP supply must be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON
and DSP power domains.
CV_DD
CV_DDDSP
Figure 6-4. DSP Host-Boot Mode Core Supply Timings
Once the CV_DD supply has been powered up, the I/O supplies may be powered up. Table 6-2 and
Figure 6-5 show the power-on sequence timing requirements for the Core vs. I/O power-up. DV_DDXX is
used to denote all I/O supplies. Note: the DV_DDXX supply power-up is specified relative to the CV_DD supply
power-up, not the CV_DDDSP supply.
Table 6-2. I/O Supply Power-On Timing Requirements (see Figure 6-5)
NO.
1
t_d(CVDD-DVDD)
Delay time, CV_DD supply ready to DV_DDXX supply ramp start
MIN MAX UNIT
0 100 ms
CV_DD
(A)
DV_DDXX
Note A: DV_DDXX denotes all I/O supplies.
Figure 6-5. I/O Supply Timings
There is not a specific power-up sequence that must be followed with respect to the order of the power-up
of the DV_DD18, DV_DDR2, and DV_DD33 supplies. Once the CV_DD supply is powered up and the t_{d(CVDD-DVDDXX)}
specification is met, the DV_DD18, DV_DDR2, and DV_DD33 supplies may be powered up in any order of
preference. All other supplies may also be powered up in any order of preference once the t_{d(CVDD-DVDDXX)}
specification has been met.
88
Peripheral and Electrical Specifications
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