SM320DM6446-HIREL_15 Datasheet, PDF (5/228 Pages) Texas Instruments – Digital Media System-on-Chip

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1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
SM320DM6446
Digital Media System-on-Chip
SPRS607A – JUNE 2009 – REVISED JUNE 2009
Input
Clock(s)
JTAG Interface
Video-Imaging
Coprocessor (VICP)
System Control ARM Subsystem
DSP Subsystem
PLLs/Clock
Generator
Power/Sleep
Controller
Pin
Multiplexing
ARM926EJ-S CPU
16 KB 8 KB
I-Cache D-Cache
16 KB RAM
16 KB ROM
C64x+t DSP CPU
64 KB L2 RAM
32 KB 80 KB
L1 Pgm L1 Data
BT.656,
Y/C,
Raw (Bayer)
Video Processing Subsystem (VPSS)
Front End
Back End
CCD
Resizer
Controller Histogram/
Video
3A
Interface Preview
On-Screen Video ^{10b DAC}
Display Encoder 10b DAC
(OSD) (VENC) _{10b DAC}
10b DAC
8b BT.656,
Y/C,
24b RGB
NTSC/
PAL,
S-Video,
RGB,
YPbPr
Switched Central Resource (SCR)
Peripherals
Serial Interfaces
System
EDMA
Audio
Serial
I²C
Port
Connectivity
USB 2.0
PHY
VLYNQ
EMAC
With
MDIO
SPI
HPI
UART
General-
Purpose
Timer
Watchdog
Timer
Program/Data Storage
PWM
DDR2 Async EMIF/ ATA/
Mem Ctlr
NAND/
Compact
(16b/32b) SmartMedia Flash
MMC/
SD/
SDIO
Figure 1-1. TMS320DM6446 Functional Block Diagram
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Digital Media System-on-Chip (DMSoC)
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